The present invention relates to data processing systems and, in particular, to a technique for automatically resetting and reinitializing a clocking subsystem of a data processing system.
Conventional data processing systems may utilize a phase locked loop (PLL) circuit in a clocking subsystem to recover and phase-align a clock signal that may be transmitted from a forwarded clocking domain to a synchronous clocking domain of a data processing system. The PLL is a closed loop frequency control circuit that performs its function by detecting the phase difference between an input clock signal and an output signal generated by a voltage-controlled oscillator (VCO). A problem with the use of a PLL in such an application is that when the input clock signal is applied to the circuit, it may not automatically become operational. That is, there are typically a number of input parameters that must be configured prior to proper operation of the PLL. These parameters may be adjusted with the use of external jumpers that may be changed as process modifications occur with respect to, e.g., an application specific integrated circuit (ASIC) within which the PLL may be embedded. Alternatively, the input parameters may be adjusted by internal logic that does not rely upon proper PLL operation to set and adjust such parameters.
In an application in which a PLL-based clocking subsystem is used in an input/output (I/O) subsystem of a data processing system, the output clock signal from the PLL is used to activate (i.e., clock) logic contained in an I/O interface circuit of the I/O subsystem. The logic contained in the I/O interface between a processor and I/O subsystem is generally non-operational until the clock signals delivered from the PLL are synchronized to enable transmission of commands between the processor and I/O subsystem. A server management subsystem within the data processing system may be unable to initialize any circuits within the I/O interface nor access any registers, e.g., control status registers (CSRs) within that interface without adding unnecessary complexity to the I/O interface and management subsystem.
Another way of initializing the circuitry within the I/O interface involves the use of special signals between the processor and I/O interface. This approach requires the use of different cables to accommodate those signals and, thus, obviates the ability to re-use similar cables between processors, and between processors and I/O subsystems, thereby creating a complicated cabling arrangement. Moreover, data processing systems, such as high performance server computers, typically utilize synchronous clock forwarded interface circuits to provide high data bandwidth on relatively narrow interconnects or links associated with the interface circuits. Clock forwarding is a technique in which data signals are accompanied by clock signals. It is thus desirable to keep the interfaces between the processors and I/O subsystems (in particular the I/O interfaces) similar to thereby enable the use of similar parts, such as cables, in a low cost manner.
The present invention is generally directed to a circuit configured to initialize a PLL within a clocking subsystem upon startup and re-initialize the PLL in the absence (or loss) of forwarded clock signals propagating between a processor and I/O interface. These clock signals may stop propagating as a result of failures in the cable coupling a processor to an I/O interface or faults in the logic circuitry of the I/O interface. All input signals received at the PLL must be preconfigured and stable prior to proper functioning of the PLL, particularly one that is embedded in an ASIC. In addition, the forwarded clock signals received at the PLL must be stable prior to initial startup of the PLL circuit. Therefore, a reset input to the PLL cannot be released until the input clock signal is stable and the other input signals are stable. As a result, the present invention is directed to a technique that enables detection of the forwarded clock signals received at a PLL and that activates (brings up) the PLL in a predetermined sequence that comports with the specifications and requirements of the vendor""s PLL.
The present invention is directed to a circuit for automatically resetting and initializing a clocking subsystem within an input/output (I/O) interface of a data processing system. The novel initialization/reset logic circuit is contained within the I/O interface and clock signals (i.e., clock forwarded clock signals) are provided from a clock source of the data processing system to the initialization/reset logic circuit. In the illustrative embodiment described herein, the I/O interface is preferably implemented as an application specific integrated circuit (ASIC) and the clock source is preferably a processor of the system.
In accordance with the invention, the PLL of the initialization/reset logic circuit includes a plurality of inputs, such as a reference clock input for receiving forwarded clock signals from the processor and a reset input for receiving a reset signal that resets the PLL, along with an output that delivers an ASIC clock that is phased-aligned to the forwarded clock. The initialization/reset logic circuit also comprises a counter having a plurality of inputs, including a clock input that receives the forwarded clock signals, a first reset input that receives a reset signal generated by the initialization/reset logic and a second reset input that receives an external reset signal generated by a voltage monitor device in response to module power transitions, e.g., the absence of DC OK. Outputs of the counter comprise a first reset output for delivering global (xe2x80x9cASICxe2x80x9d) reset signals to the I/O interface, a second reset output for delivering PLL reset signals and a third reset output for delivering an error control status register (CSR) reset signal to a set of error registers. A timer circuit receives the forwarded clock signals at its input and generates 20 microsecond (xcexcsec), pulsed timer signals that are delivered to a watchdog timer circuit. The watchdog timer is configured to detect the presence (or absence) of the pulsed timer signals at its input. A reset output of the watchdog timer delivers reset signals to the reset input of the counter.
Before the forwarded clock signals are received at the timer circuit and, thus, in the absence of the 20 xcexcsec signal, the watchdog timer xe2x80x9ctimes outxe2x80x9d and periodically asserts a reset signal to the counter which, in turn, provides reset signals to the PLL and various logic circuitry of the ASIC. Notably, however, assertion of the reset signal does not reset the 20 xcexcsec timer circuit or the contents of the error (CSR) registers. Once the clock signals are received at the timer circuit and the 20 xcexcsec pulsed timer signals are generated, the watchdog timer halts issuance of the periodic reset signals. These received clock signals also initiate logical functions that initially place the PLL in a reset state waiting for the PLL reference clock input and its other input signals to stabilize.
After a predetermined period of time, the PLL reset input signal is released and a second timer begins. After a subsequent predetermined period of time that allows the PLL to xe2x80x9clockxe2x80x9d to the incoming clock signals, phased-aligned clock signals are distributed throughout the I/O interface. Thereafter, the second timer expires and releases the global ASIC reset signal, thereby initializing the I/O interface to a predefined state. At this point, communication between the processor and the ASIC is possible. In certain cases, clock signals received from the processor may be stopped intentionally or due to errors or failures; as a result, communication between the processor and the ASIC is no longer possible. Consequently, the PLL no longer operates correctly, if at all, and requires execution of the initialization sequence described above. The watchdog timer senses the absence of the 20 xcexcsec signal and reinitializes the ASIC and PLL, while CSR error state is maintained, without any other external intervention.
Advantageously, the present invention provides a means for initializing a PLL-based clocking system without the use of special signals and control mechanisms. Prior attempts to initialize such a subsystem involved a system global reset signal means and/or a local reset signaling means operating independently of the unit to be reset. The present invention provides a simpler solution that requires no external reset mechanism and that self-initializes the PLL, initializes the I/O interface and retains critical error state despite the loss and subsequent restart of the forwarded clock signals. In addition, the initialization/reset logic circuit reduces part counts and enables an inexpensive implementation.